diff options
author | Matt A. Tobin <email@mattatobin.com> | 2020-02-28 18:00:45 -0500 |
---|---|---|
committer | Matt A. Tobin <email@mattatobin.com> | 2020-02-28 18:00:45 -0500 |
commit | 65b37410ca38005bd6f4c9470c93a49cd12ad368 (patch) | |
tree | c65f22f3ed2fda8b9b3ff36c029020bd1500d946 /js | |
parent | 6a3d5769d01ec1a8dd56ea79aec2df91b801ce02 (diff) | |
download | UXP-65b37410ca38005bd6f4c9470c93a49cd12ad368.tar UXP-65b37410ca38005bd6f4c9470c93a49cd12ad368.tar.gz UXP-65b37410ca38005bd6f4c9470c93a49cd12ad368.tar.lz UXP-65b37410ca38005bd6f4c9470c93a49cd12ad368.tar.xz UXP-65b37410ca38005bd6f4c9470c93a49cd12ad368.zip |
Revert "Issue #190 - Part 1: Remove XP_IOS conditional code"
This reverts commit 6a3d5769d01ec1a8dd56ea79aec2df91b801ce02.
Diffstat (limited to 'js')
-rw-r--r-- | js/src/irregexp/NativeRegExpMacroAssembler.cpp | 13 | ||||
-rw-r--r-- | js/src/jit/ExecutableAllocator.h | 7 | ||||
-rw-r--r-- | js/src/jit/arm/Architecture-arm.h | 11 |
3 files changed, 28 insertions, 3 deletions
diff --git a/js/src/irregexp/NativeRegExpMacroAssembler.cpp b/js/src/irregexp/NativeRegExpMacroAssembler.cpp index f452de6ba..0fb507297 100644 --- a/js/src/irregexp/NativeRegExpMacroAssembler.cpp +++ b/js/src/irregexp/NativeRegExpMacroAssembler.cpp @@ -132,6 +132,14 @@ NativeRegExpMacroAssembler::GenerateCode(JSContext* cx, bool match_only) pushedNonVolatileRegisters++; } +#if defined(XP_IOS) && defined(JS_CODEGEN_ARM) + // The stack is 4-byte aligned on iOS, force 8-byte alignment. + masm.movePtr(StackPointer, temp0); + masm.andPtr(Imm32(~7), StackPointer); + masm.push(temp0); + masm.push(temp0); +#endif + #ifndef JS_CODEGEN_X86 // The InputOutputData* is stored as an argument, save it on the stack // above the frame. @@ -398,6 +406,11 @@ NativeRegExpMacroAssembler::GenerateCode(JSContext* cx, bool match_only) masm.freeStack(frameSize); #endif +#if defined(XP_IOS) && defined(JS_CODEGEN_ARM) + masm.pop(temp0); + masm.movePtr(temp0, StackPointer); +#endif + // Restore non-volatile registers which were saved on entry. for (GeneralRegisterBackwardIterator iter(savedNonVolatileRegisters); iter.more(); ++iter) masm.Pop(*iter); diff --git a/js/src/jit/ExecutableAllocator.h b/js/src/jit/ExecutableAllocator.h index 20f11f14f..30eccd12e 100644 --- a/js/src/jit/ExecutableAllocator.h +++ b/js/src/jit/ExecutableAllocator.h @@ -69,7 +69,7 @@ extern "C" void sync_instruction_memory(caddr_t v, u_int len); #include <sys/cachectl.h> #endif -#ifdef JS_CODEGEN_ARM +#if defined(JS_CODEGEN_ARM) && defined(XP_IOS) #include <libkern/OSCacheControl.h> #endif @@ -256,6 +256,11 @@ class ExecutableAllocator { __clear_cache(code, reinterpret_cast<char*>(code) + size); } +#elif (defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64)) && defined(XP_IOS) + static void cacheFlush(void* code, size_t size) + { + sys_icache_invalidate(code, size); + } #elif defined(JS_CODEGEN_ARM) && (defined(__linux__) || defined(ANDROID)) && defined(__GNUC__) static void cacheFlush(void* code, size_t size) { diff --git a/js/src/jit/arm/Architecture-arm.h b/js/src/jit/arm/Architecture-arm.h index 0c47c0250..5e3db5ae2 100644 --- a/js/src/jit/arm/Architecture-arm.h +++ b/js/src/jit/arm/Architecture-arm.h @@ -17,7 +17,7 @@ // GCC versions 4.6 and above define __ARM_PCS_VFP to denote a hard-float // ABI target. The iOS toolchain doesn't define anything specific here, // but iOS always supports VFP. -#ifdef__ARM_PCS_VFP +#if defined(__ARM_PCS_VFP) || defined(XP_IOS) #define JS_CODEGEN_ARM_HARDFP #endif @@ -114,7 +114,12 @@ class Registers (1 << r0) | (1 << r1) | (1 << Registers::r2) | - (1 << Registers::r3); + (1 << Registers::r3) +#if defined(XP_IOS) + // per https://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/Articles/ARMv6FunctionCallingConventions.html#//apple_ref/doc/uid/TP40009021-SW4 + | (1 << Registers::r9) +#endif + ; static const SetType NonVolatileMask = (1 << Registers::r4) | @@ -122,7 +127,9 @@ class Registers (1 << Registers::r6) | (1 << Registers::r7) | (1 << Registers::r8) | +#if !defined(XP_IOS) (1 << Registers::r9) | +#endif (1 << Registers::r10) | (1 << Registers::r11) | (1 << Registers::r12) | |