diff options
Diffstat (limited to 'media/ffvpx/libavutil/x86/cpu.c')
| -rw-r--r-- | media/ffvpx/libavutil/x86/cpu.c | 37 |
1 files changed, 35 insertions, 2 deletions
diff --git a/media/ffvpx/libavutil/x86/cpu.c b/media/ffvpx/libavutil/x86/cpu.c index f3a49c677..f33088c8c 100644 --- a/media/ffvpx/libavutil/x86/cpu.c +++ b/media/ffvpx/libavutil/x86/cpu.c @@ -28,7 +28,7 @@ #include "libavutil/cpu.h" #include "libavutil/cpu_internal.h" -#if HAVE_YASM +#if HAVE_X86ASM #define cpuid(index, eax, ebx, ecx, edx) \ ff_cpu_cpuid(index, &eax, &ebx, &ecx, &edx) @@ -66,7 +66,7 @@ #define cpuid_test() 1 -#elif HAVE_YASM +#elif HAVE_X86ASM #define cpuid_test ff_cpu_cpuid_test @@ -221,9 +221,42 @@ int ff_get_cpu_flags_x86(void) * functions on the Atom. */ if (family == 6 && model == 28) rval |= AV_CPU_FLAG_ATOM; + + /* Conroe has a slow shuffle unit. Check the model number to ensure not + * to include crippled low-end Penryns and Nehalems that lack SSE4. */ + if ((rval & AV_CPU_FLAG_SSSE3) && !(rval & AV_CPU_FLAG_SSE4) && + family == 6 && model < 23) + rval |= AV_CPU_FLAG_SSSE3SLOW; } #endif /* cpuid */ return rval; } + +size_t ff_get_cpu_max_align_x86(void) +{ + int flags = av_get_cpu_flags(); + + if (flags & (AV_CPU_FLAG_AVX2 | + AV_CPU_FLAG_AVX | + AV_CPU_FLAG_XOP | + AV_CPU_FLAG_FMA4 | + AV_CPU_FLAG_FMA3 | + AV_CPU_FLAG_AVXSLOW)) + return 32; + if (flags & (AV_CPU_FLAG_AESNI | + AV_CPU_FLAG_SSE42 | + AV_CPU_FLAG_SSE4 | + AV_CPU_FLAG_SSSE3 | + AV_CPU_FLAG_SSE3 | + AV_CPU_FLAG_SSE2 | + AV_CPU_FLAG_SSE | + AV_CPU_FLAG_ATOM | + AV_CPU_FLAG_SSSE3SLOW | + AV_CPU_FLAG_SSE3SLOW | + AV_CPU_FLAG_SSE2SLOW)) + return 16; + + return 8; +} |