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-rw-r--r--js/src/jit/mips-shared/Assembler-mips-shared.h10
-rw-r--r--js/src/jit/mips-shared/CodeGenerator-mips-shared.cpp45
-rw-r--r--js/src/jit/mips-shared/MacroAssembler-mips-shared.cpp36
-rw-r--r--js/src/jit/mips-shared/MacroAssembler-mips-shared.h4
4 files changed, 64 insertions, 31 deletions
diff --git a/js/src/jit/mips-shared/Assembler-mips-shared.h b/js/src/jit/mips-shared/Assembler-mips-shared.h
index 4cfb30117..1640fdafc 100644
--- a/js/src/jit/mips-shared/Assembler-mips-shared.h
+++ b/js/src/jit/mips-shared/Assembler-mips-shared.h
@@ -1550,7 +1550,15 @@ class InstGS : public Instruction
inline bool
IsUnaligned(const wasm::MemoryAccessDesc& access)
{
- return access.align() && access.align() < access.byteSize();
+ if (!access.align())
+ return false;
+
+#ifdef JS_CODEGEN_MIPS32
+ if (access.type() == Scalar::Int64 && access.align() >= 4)
+ return false;
+#endif
+
+ return access.align() < access.byteSize();
}
} // namespace jit
diff --git a/js/src/jit/mips-shared/CodeGenerator-mips-shared.cpp b/js/src/jit/mips-shared/CodeGenerator-mips-shared.cpp
index 2526fc237..d43dbbf38 100644
--- a/js/src/jit/mips-shared/CodeGenerator-mips-shared.cpp
+++ b/js/src/jit/mips-shared/CodeGenerator-mips-shared.cpp
@@ -1919,12 +1919,14 @@ CodeGeneratorMIPSShared::emitWasmLoad(T* lir)
Register temp = ToRegister(lir->getTemp(1));
if (isFloat) {
+ FloatRegister output = ToFloatRegister(lir->output());
+
if (byteSize == 4)
- masm.loadUnalignedFloat32(address, temp, ToFloatRegister(lir->output()));
+ masm.loadUnalignedFloat32(mir->access(), address, temp, output);
else
- masm.loadUnalignedDouble(address, temp, ToFloatRegister(lir->output()));
+ masm.loadUnalignedDouble(mir->access(), address, temp, output);
} else {
- masm.ma_load_unaligned(ToRegister(lir->output()), address, temp,
+ masm.ma_load_unaligned(mir->access(), ToRegister(lir->output()), address, temp,
static_cast<LoadStoreSize>(8 * byteSize),
isSigned ? SignExtend : ZeroExtend);
}
@@ -1934,16 +1936,20 @@ CodeGeneratorMIPSShared::emitWasmLoad(T* lir)
}
if (isFloat) {
- if (byteSize == 4)
- masm.loadFloat32(address, ToFloatRegister(lir->output()));
- else
- masm.loadDouble(address, ToFloatRegister(lir->output()));
+ FloatRegister output = ToFloatRegister(lir->output());
+
+ if (byteSize == 4) {
+ masm.loadFloat32(address, output);
+ } else {
+ masm.computeScaledAddress(address, SecondScratchReg);
+ masm.as_ld(output, SecondScratchReg, 0);
+ }
} else {
masm.ma_load(ToRegister(lir->output()), address,
static_cast<LoadStoreSize>(8 * byteSize),
isSigned ? SignExtend : ZeroExtend);
}
-
+ masm.append(mir->access(), masm.size() - 4, masm.framePushed());
masm.memoryBarrier(mir->access().barrierAfter());
}
@@ -2004,12 +2010,14 @@ CodeGeneratorMIPSShared::emitWasmStore(T* lir)
Register temp = ToRegister(lir->getTemp(1));
if (isFloat) {
+ FloatRegister value = ToFloatRegister(lir->value());
+
if (byteSize == 4)
- masm.storeUnalignedFloat32(ToFloatRegister(lir->value()), temp, address);
+ masm.storeUnalignedFloat32(mir->access(), value, temp, address);
else
- masm.storeUnalignedDouble(ToFloatRegister(lir->value()), temp, address);
+ masm.storeUnalignedDouble(mir->access(), value, temp, address);
} else {
- masm.ma_store_unaligned(ToRegister(lir->value()), address, temp,
+ masm.ma_store_unaligned(mir->access(), ToRegister(lir->value()), address, temp,
static_cast<LoadStoreSize>(8 * byteSize),
isSigned ? SignExtend : ZeroExtend);
}
@@ -2019,16 +2027,23 @@ CodeGeneratorMIPSShared::emitWasmStore(T* lir)
}
if (isFloat) {
+ FloatRegister value = ToFloatRegister(lir->value());
+
if (byteSize == 4) {
- masm.storeFloat32(ToFloatRegister(lir->value()), address);
- } else
- masm.storeDouble(ToFloatRegister(lir->value()), address);
+ masm.storeFloat32(value, address);
+ } else {
+ // For time being storeDouble for mips32 uses two store instructions,
+ // so we emit only one to get correct behavior in case of OOB access.
+ masm.computeScaledAddress(address, SecondScratchReg);
+ masm.as_sd(value, SecondScratchReg, 0);
+ }
} else {
masm.ma_store(ToRegister(lir->value()), address,
static_cast<LoadStoreSize>(8 * byteSize),
isSigned ? SignExtend : ZeroExtend);
}
-
+ // Only the last emitted instruction is a memory access.
+ masm.append(mir->access(), masm.size() - 4, masm.framePushed());
masm.memoryBarrier(mir->access().barrierAfter());
}
diff --git a/js/src/jit/mips-shared/MacroAssembler-mips-shared.cpp b/js/src/jit/mips-shared/MacroAssembler-mips-shared.cpp
index 3665f3072..0676863b9 100644
--- a/js/src/jit/mips-shared/MacroAssembler-mips-shared.cpp
+++ b/js/src/jit/mips-shared/MacroAssembler-mips-shared.cpp
@@ -463,7 +463,7 @@ MacroAssemblerMIPSShared::ma_load(Register dest, const BaseIndex& src,
}
void
-MacroAssemblerMIPSShared::ma_load_unaligned(Register dest, const BaseIndex& src, Register temp,
+MacroAssemblerMIPSShared::ma_load_unaligned(const wasm::MemoryAccessDesc& access, Register dest, const BaseIndex& src, Register temp,
LoadStoreSize size, LoadStoreExtension extension)
{
int16_t lowOffset, hiOffset;
@@ -477,36 +477,41 @@ MacroAssemblerMIPSShared::ma_load_unaligned(Register dest, const BaseIndex& src,
hiOffset = Imm16(src.offset + size / 8 - 1).encode();
} else {
ma_li(ScratchRegister, Imm32(src.offset));
- as_daddu(ScratchRegister, SecondScratchReg, ScratchRegister);
+ asMasm().addPtr(SecondScratchReg, ScratchRegister);
base = ScratchRegister;
lowOffset = Imm16(0).encode();
hiOffset = Imm16(size / 8 - 1).encode();
}
+ BufferOffset load;
switch (size) {
case SizeHalfWord:
- as_lbu(dest, base, lowOffset);
if (extension != ZeroExtend)
- as_lbu(temp, base, hiOffset);
+ load = as_lbu(temp, base, hiOffset);
else
- as_lb(temp, base, hiOffset);
+ load = as_lb(temp, base, hiOffset);
+ as_lbu(dest, base, lowOffset);
as_ins(dest, temp, 8, 24);
break;
case SizeWord:
- as_lwl(dest, base, hiOffset);
+ load = as_lwl(dest, base, hiOffset);
as_lwr(dest, base, lowOffset);
#ifdef JS_CODEGEN_MIPS64
if (extension != ZeroExtend)
as_dext(dest, dest, 0, 32);
#endif
break;
+#ifdef JS_CODEGEN_MIPS64
case SizeDouble:
- as_ldl(dest, base, hiOffset);
+ load = as_ldl(dest, base, hiOffset);
as_ldr(dest, base, lowOffset);
break;
+#endif
default:
MOZ_CRASH("Invalid argument for ma_load");
}
+
+ append(access, load.getOffset(), asMasm().framePushed());
}
void
@@ -610,7 +615,7 @@ MacroAssemblerMIPSShared::ma_store(Imm32 imm, const BaseIndex& dest,
}
void
-MacroAssemblerMIPSShared::ma_store_unaligned(Register data, const BaseIndex& dest, Register temp,
+MacroAssemblerMIPSShared::ma_store_unaligned(const wasm::MemoryAccessDesc& access, Register data, const BaseIndex& dest, Register temp,
LoadStoreSize size, LoadStoreExtension extension)
{
int16_t lowOffset, hiOffset;
@@ -624,29 +629,34 @@ MacroAssemblerMIPSShared::ma_store_unaligned(Register data, const BaseIndex& des
hiOffset = Imm16(dest.offset + size / 8 - 1).encode();
} else {
ma_li(ScratchRegister, Imm32(dest.offset));
- as_daddu(ScratchRegister, SecondScratchReg, ScratchRegister);
+ asMasm().addPtr(SecondScratchReg, ScratchRegister);
base = ScratchRegister;
lowOffset = Imm16(0).encode();
hiOffset = Imm16(size / 8 - 1).encode();
}
+ BufferOffset store;
switch (size) {
case SizeHalfWord:
- as_sb(data, base, lowOffset);
as_ext(temp, data, 8, 8);
- as_sb(temp, base, hiOffset);
+ store = as_sb(temp, base, hiOffset);
+ as_sb(data, base, lowOffset);
break;
case SizeWord:
- as_swl(data, base, hiOffset);
+ store = as_swl(data, base, hiOffset);
as_swr(data, base, lowOffset);
break;
+#ifdef JS_CODEGEN_MIPS64
case SizeDouble:
- as_sdl(data, base, hiOffset);
+ store = as_sdl(data, base, hiOffset);
as_sdr(data, base, lowOffset);
break;
+#endif
default:
MOZ_CRASH("Invalid argument for ma_store");
}
+
+ append(access, store.getOffset(), asMasm().framePushed());
}
void
diff --git a/js/src/jit/mips-shared/MacroAssembler-mips-shared.h b/js/src/jit/mips-shared/MacroAssembler-mips-shared.h
index cd75b2e37..4f5dcd309 100644
--- a/js/src/jit/mips-shared/MacroAssembler-mips-shared.h
+++ b/js/src/jit/mips-shared/MacroAssembler-mips-shared.h
@@ -108,7 +108,7 @@ class MacroAssemblerMIPSShared : public Assembler
// load
void ma_load(Register dest, const BaseIndex& src, LoadStoreSize size = SizeWord,
LoadStoreExtension extension = SignExtend);
- void ma_load_unaligned(Register dest, const BaseIndex& src, Register temp,
+ void ma_load_unaligned(const wasm::MemoryAccessDesc& access, Register dest, const BaseIndex& src, Register temp,
LoadStoreSize size, LoadStoreExtension extension);
// store
@@ -116,7 +116,7 @@ class MacroAssemblerMIPSShared : public Assembler
LoadStoreExtension extension = SignExtend);
void ma_store(Imm32 imm, const BaseIndex& dest, LoadStoreSize size = SizeWord,
LoadStoreExtension extension = SignExtend);
- void ma_store_unaligned(Register data, const BaseIndex& dest, Register temp,
+ void ma_store_unaligned(const wasm::MemoryAccessDesc& access, Register data, const BaseIndex& dest, Register temp,
LoadStoreSize size, LoadStoreExtension extension);
// arithmetic based ops
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-17 09:19:05 +0000