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| author | wolfbeast <mcwerewolf@wolfbeast.com> | 2019-03-29 16:04:01 +0100 |
|---|---|---|
| committer | wolfbeast <mcwerewolf@wolfbeast.com> | 2019-03-29 16:04:01 +0100 |
| commit | 88083f8c683c18f4de68a20c863a82a9da65db8f (patch) | |
| tree | 926656892d9d80260da02ea8ea71031b140c51df /other-licenses/7zstub/src/Asm/arm/7zCrcOpt.asm | |
| parent | f999f544aad04069b03704d994a99352263f600b (diff) | |
| parent | 843e4ceffd6ce21a6e6db37419335eafdc543e18 (diff) | |
| download | UXP-88083f8c683c18f4de68a20c863a82a9da65db8f.tar UXP-88083f8c683c18f4de68a20c863a82a9da65db8f.tar.gz UXP-88083f8c683c18f4de68a20c863a82a9da65db8f.tar.lz UXP-88083f8c683c18f4de68a20c863a82a9da65db8f.tar.xz UXP-88083f8c683c18f4de68a20c863a82a9da65db8f.zip | |
Merge branch 'master' into Sync-weave
Diffstat (limited to 'other-licenses/7zstub/src/Asm/arm/7zCrcOpt.asm')
| -rw-r--r-- | other-licenses/7zstub/src/Asm/arm/7zCrcOpt.asm | 100 |
1 files changed, 100 insertions, 0 deletions
diff --git a/other-licenses/7zstub/src/Asm/arm/7zCrcOpt.asm b/other-licenses/7zstub/src/Asm/arm/7zCrcOpt.asm new file mode 100644 index 000000000..f008d658c --- /dev/null +++ b/other-licenses/7zstub/src/Asm/arm/7zCrcOpt.asm @@ -0,0 +1,100 @@ + CODE32
+
+ EXPORT |CrcUpdateT4@16|
+
+ AREA |.text|, CODE, ARM
+
+ MACRO
+ CRC32_STEP_1
+
+ ldrb r4, [r1], #1
+ subs r2, r2, #1
+ eor r4, r4, r0
+ and r4, r4, #0xFF
+ ldr r4, [r3, +r4, lsl #2]
+ eor r0, r4, r0, lsr #8
+
+ MEND
+
+
+ MACRO
+ CRC32_STEP_4 $STREAM_WORD
+
+ eor r7, r7, r8
+ eor r7, r7, r9
+ eor r0, r0, r7
+ eor r0, r0, $STREAM_WORD
+ ldr $STREAM_WORD, [r1], #4
+
+ and r7, r0, #0xFF
+ and r8, r0, #0xFF00
+ and r9, r0, #0xFF0000
+ and r0, r0, #0xFF000000
+
+ ldr r7, [r6, +r7, lsl #2]
+ ldr r8, [r5, +r8, lsr #6]
+ ldr r9, [r4, +r9, lsr #14]
+ ldr r0, [r3, +r0, lsr #22]
+
+ MEND
+
+
+|CrcUpdateT4@16| PROC
+
+ stmdb sp!, {r4-r11, lr}
+ cmp r2, #0
+ beq |$fin|
+
+|$v1|
+ tst r1, #7
+ beq |$v2|
+ CRC32_STEP_1
+ bne |$v1|
+
+|$v2|
+ cmp r2, #16
+ blo |$v3|
+
+ ldr r10, [r1], #4
+ ldr r11, [r1], #4
+
+ add r4, r3, #0x400
+ add r5, r3, #0x800
+ add r6, r3, #0xC00
+
+ mov r7, #0
+ mov r8, #0
+ mov r9, #0
+
+ sub r2, r2, #16
+
+|$loop|
+ ; pld [r1, #0x40]
+
+ CRC32_STEP_4 r10
+ CRC32_STEP_4 r11
+
+ subs r2, r2, #8
+ bhs |$loop|
+
+ sub r1, r1, #8
+ add r2, r2, #16
+
+ eor r7, r7, r8
+ eor r7, r7, r9
+ eor r0, r0, r7
+
+|$v3|
+ cmp r2, #0
+ beq |$fin|
+
+|$v4|
+ CRC32_STEP_1
+ bne |$v4|
+
+|$fin|
+ ldmia sp!, {r4-r11, pc}
+
+|CrcUpdateT4@16| ENDP
+
+ END
|