summaryrefslogtreecommitdiffstats
path: root/js/src/jit
diff options
context:
space:
mode:
authorJiaxun Yang <jiaxun.yang@flygoat.com>2020-05-12 12:40:13 +0800
committerMoonchild <moonchild@palemoon.org>2020-05-20 14:03:04 +0000
commitf411e027165e7d95a6119d8dabbc15e4f3a206e8 (patch)
treef599523af694eab863e9c22be2e26f434c4ba15d /js/src/jit
parenta34d02924c825b17af0fd505d8fdb890d5ae5dc1 (diff)
downloadUXP-f411e027165e7d95a6119d8dabbc15e4f3a206e8.tar
UXP-f411e027165e7d95a6119d8dabbc15e4f3a206e8.tar.gz
UXP-f411e027165e7d95a6119d8dabbc15e4f3a206e8.tar.lz
UXP-f411e027165e7d95a6119d8dabbc15e4f3a206e8.tar.xz
UXP-f411e027165e7d95a6119d8dabbc15e4f3a206e8.zip
Bug 1330942 - move MemoryAccessDesc::isUnaligned to the ARM/MIPS platform layer
Tag: #1542
Diffstat (limited to 'js/src/jit')
-rw-r--r--js/src/jit/arm/Assembler-arm.cpp12
-rw-r--r--js/src/jit/arm/Assembler-arm.h2
-rw-r--r--js/src/jit/arm/Lowering-arm.cpp4
-rw-r--r--js/src/jit/mips-shared/Assembler-mips-shared.h6
-rw-r--r--js/src/jit/mips-shared/CodeGenerator-mips-shared.cpp4
-rw-r--r--js/src/jit/mips-shared/Lowering-mips-shared.cpp4
-rw-r--r--js/src/jit/mips32/CodeGenerator-mips32.cpp4
-rw-r--r--js/src/jit/mips64/CodeGenerator-mips64.cpp4
-rw-r--r--js/src/jit/shared/Assembler-shared.h1
9 files changed, 30 insertions, 11 deletions
diff --git a/js/src/jit/arm/Assembler-arm.cpp b/js/src/jit/arm/Assembler-arm.cpp
index 1e20da1c8..b231128c5 100644
--- a/js/src/jit/arm/Assembler-arm.cpp
+++ b/js/src/jit/arm/Assembler-arm.cpp
@@ -171,6 +171,18 @@ ABIArgGenerator::next(MIRType type)
return softNext(type);
}
+bool
+js::jit::IsUnaligned(const wasm::MemoryAccessDesc& access)
+{
+ if (!access.align())
+ return false;
+
+ if (access.type() == Scalar::Float64 && access.align() >= 4)
+ return false;
+
+ return access.align() < access.byteSize();
+}
+
// Encode a standard register when it is being used as src1, the dest, and an
// extra register. These should never be called with an InvalidReg.
uint32_t
diff --git a/js/src/jit/arm/Assembler-arm.h b/js/src/jit/arm/Assembler-arm.h
index 8bb754a50..ecfb83b42 100644
--- a/js/src/jit/arm/Assembler-arm.h
+++ b/js/src/jit/arm/Assembler-arm.h
@@ -108,6 +108,8 @@ class ABIArgGenerator
uint32_t stackBytesConsumedSoFar() const { return stackOffset_; }
};
+bool IsUnaligned(const wasm::MemoryAccessDesc& access);
+
static constexpr Register ABINonArgReg0 = r4;
static constexpr Register ABINonArgReg1 = r5;
static constexpr Register ABINonArgReg2 = r6;
diff --git a/js/src/jit/arm/Lowering-arm.cpp b/js/src/jit/arm/Lowering-arm.cpp
index c26680116..b9440816a 100644
--- a/js/src/jit/arm/Lowering-arm.cpp
+++ b/js/src/jit/arm/Lowering-arm.cpp
@@ -613,7 +613,7 @@ LIRGeneratorARM::visitWasmLoad(MWasmLoad* ins)
LAllocation ptr = useRegisterAtStart(base);
- if (ins->access().isUnaligned()) {
+ if (IsUnaligned(ins->access())) {
// Unaligned access expected! Revert to a byte load.
LDefinition ptrCopy = tempCopy(base, 0);
@@ -662,7 +662,7 @@ LIRGeneratorARM::visitWasmStore(MWasmStore* ins)
LAllocation ptr = useRegisterAtStart(base);
- if (ins->access().isUnaligned()) {
+ if (IsUnaligned(ins->access())) {
// Unaligned access expected! Revert to a byte store.
LDefinition ptrCopy = tempCopy(base, 0);
diff --git a/js/src/jit/mips-shared/Assembler-mips-shared.h b/js/src/jit/mips-shared/Assembler-mips-shared.h
index 5a47eb1dc..4cfb30117 100644
--- a/js/src/jit/mips-shared/Assembler-mips-shared.h
+++ b/js/src/jit/mips-shared/Assembler-mips-shared.h
@@ -1547,6 +1547,12 @@ class InstGS : public Instruction
{ }
};
+inline bool
+IsUnaligned(const wasm::MemoryAccessDesc& access)
+{
+ return access.align() && access.align() < access.byteSize();
+}
+
} // namespace jit
} // namespace js
diff --git a/js/src/jit/mips-shared/CodeGenerator-mips-shared.cpp b/js/src/jit/mips-shared/CodeGenerator-mips-shared.cpp
index 1a5a3987b..2526fc237 100644
--- a/js/src/jit/mips-shared/CodeGenerator-mips-shared.cpp
+++ b/js/src/jit/mips-shared/CodeGenerator-mips-shared.cpp
@@ -1915,7 +1915,7 @@ CodeGeneratorMIPSShared::emitWasmLoad(T* lir)
BaseIndex address(HeapReg, ptr, TimesOne);
- if (mir->access().isUnaligned()) {
+ if (IsUnaligned(mir->access())) {
Register temp = ToRegister(lir->getTemp(1));
if (isFloat) {
@@ -2000,7 +2000,7 @@ CodeGeneratorMIPSShared::emitWasmStore(T* lir)
BaseIndex address(HeapReg, ptr, TimesOne);
- if (mir->access().isUnaligned()) {
+ if (IsUnaligned(mir->access())) {
Register temp = ToRegister(lir->getTemp(1));
if (isFloat) {
diff --git a/js/src/jit/mips-shared/Lowering-mips-shared.cpp b/js/src/jit/mips-shared/Lowering-mips-shared.cpp
index f328d16f7..8c78f56b7 100644
--- a/js/src/jit/mips-shared/Lowering-mips-shared.cpp
+++ b/js/src/jit/mips-shared/Lowering-mips-shared.cpp
@@ -324,7 +324,7 @@ LIRGeneratorMIPSShared::visitWasmLoad(MWasmLoad* ins)
LAllocation ptr = useRegisterAtStart(base);
- if (ins->access().isUnaligned()) {
+ if (IsUnaligned(ins->access())) {
if (ins->type() == MIRType::Int64) {
auto* lir = new(alloc()) LWasmUnalignedLoadI64(ptr, temp());
if (ins->access().offset())
@@ -367,7 +367,7 @@ LIRGeneratorMIPSShared::visitWasmStore(MWasmStore* ins)
MDefinition* value = ins->value();
LAllocation baseAlloc = useRegisterAtStart(base);
- if (ins->access().isUnaligned()) {
+ if (IsUnaligned(ins->access())) {
if (ins->type() == MIRType::Int64) {
LInt64Allocation valueAlloc = useInt64RegisterAtStart(value);
auto* lir = new(alloc()) LWasmUnalignedStoreI64(baseAlloc, valueAlloc, temp());
diff --git a/js/src/jit/mips32/CodeGenerator-mips32.cpp b/js/src/jit/mips32/CodeGenerator-mips32.cpp
index b947c14aa..33fea01ae 100644
--- a/js/src/jit/mips32/CodeGenerator-mips32.cpp
+++ b/js/src/jit/mips32/CodeGenerator-mips32.cpp
@@ -490,7 +490,7 @@ CodeGeneratorMIPS::emitWasmLoadI64(T* lir)
masm.memoryBarrier(mir->access().barrierBefore());
MOZ_ASSERT(INT64LOW_OFFSET == 0);
- if (mir->access().isUnaligned()) {
+ if (IsUnaligned(mir->access())) {
Register temp = ToRegister(lir->getTemp(1));
if (byteSize <= 4) {
@@ -577,7 +577,7 @@ CodeGeneratorMIPS::emitWasmStoreI64(T* lir)
masm.memoryBarrier(mir->access().barrierBefore());
MOZ_ASSERT(INT64LOW_OFFSET == 0);
- if (mir->access().isUnaligned()) {
+ if (IsUnaligned(mir->access())) {
Register temp = ToRegister(lir->getTemp(1));
if (byteSize <= 4) {
diff --git a/js/src/jit/mips64/CodeGenerator-mips64.cpp b/js/src/jit/mips64/CodeGenerator-mips64.cpp
index 45f0e69d7..d1b6a7a32 100644
--- a/js/src/jit/mips64/CodeGenerator-mips64.cpp
+++ b/js/src/jit/mips64/CodeGenerator-mips64.cpp
@@ -449,7 +449,7 @@ CodeGeneratorMIPS64::emitWasmLoadI64(T* lir)
masm.memoryBarrier(mir->access().barrierBefore());
- if (mir->access().isUnaligned()) {
+ if (IsUnaligned(mir->access())) {
Register temp = ToRegister(lir->getTemp(1));
masm.ma_load_unaligned(ToOutRegister64(lir).reg, BaseIndex(HeapReg, ptr, TimesOne),
@@ -514,7 +514,7 @@ CodeGeneratorMIPS64::emitWasmStoreI64(T* lir)
masm.memoryBarrier(mir->access().barrierBefore());
- if (mir->access().isUnaligned()) {
+ if (IsUnaligned(mir->access())) {
Register temp = ToRegister(lir->getTemp(1));
masm.ma_store_unaligned(ToRegister64(lir->value()).reg, BaseIndex(HeapReg, ptr, TimesOne),
diff --git a/js/src/jit/shared/Assembler-shared.h b/js/src/jit/shared/Assembler-shared.h
index 8044e75cb..258f977e3 100644
--- a/js/src/jit/shared/Assembler-shared.h
+++ b/js/src/jit/shared/Assembler-shared.h
@@ -747,7 +747,6 @@ class MemoryAccessDesc
TrapOffset trapOffset() const { return *trapOffset_; }
bool isAtomic() const { return (barrierBefore_ | barrierAfter_) != jit::MembarNobits; }
bool isSimd() const { return Scalar::isSimdType(type_); }
- bool isUnaligned() const { return align() && align() < byteSize(); }
bool isPlainAsmJS() const { return !hasTrap(); }
void clearOffset() { offset_ = 0; }