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author | trav90 <travawine@palemoon.org> | 2018-10-17 05:59:08 -0500 |
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committer | trav90 <travawine@palemoon.org> | 2018-10-17 05:59:08 -0500 |
commit | df9477dfa60ebb5d31bc142e58ce46535c17abce (patch) | |
tree | c4fdd5d1b09d08c0514f208246260fc87372cb56 /third_party/aom/av1/common/reconintra.h | |
parent | 0cc51bc106250988cc3b89cb5d743a5af52cd35a (diff) | |
download | UXP-df9477dfa60ebb5d31bc142e58ce46535c17abce.tar UXP-df9477dfa60ebb5d31bc142e58ce46535c17abce.tar.gz UXP-df9477dfa60ebb5d31bc142e58ce46535c17abce.tar.lz UXP-df9477dfa60ebb5d31bc142e58ce46535c17abce.tar.xz UXP-df9477dfa60ebb5d31bc142e58ce46535c17abce.zip |
Update aom to slightly newer commit ID
Diffstat (limited to 'third_party/aom/av1/common/reconintra.h')
-rw-r--r-- | third_party/aom/av1/common/reconintra.h | 50 |
1 files changed, 38 insertions, 12 deletions
diff --git a/third_party/aom/av1/common/reconintra.h b/third_party/aom/av1/common/reconintra.h index 7ee0c495e..fbcb7f9b4 100644 --- a/third_party/aom/av1/common/reconintra.h +++ b/third_party/aom/av1/common/reconintra.h @@ -19,6 +19,20 @@ extern "C" { #endif +#if CONFIG_DPCM_INTRA +static INLINE int av1_use_dpcm_intra(int plane, PREDICTION_MODE mode, + TX_TYPE tx_type, + const MB_MODE_INFO *const mbmi) { + (void)mbmi; + (void)plane; +#if CONFIG_EXT_INTRA + if (mbmi->sb_type >= BLOCK_8X8 && mbmi->angle_delta[plane != 0]) return 0; +#endif // CONFIG_EXT_INTRA + return (mode == V_PRED && (tx_type == IDTX || tx_type == H_DCT)) || + (mode == H_PRED && (tx_type == IDTX || tx_type == V_DCT)); +} +#endif // CONFIG_DPCM_INTRA + void av1_init_intra_predictors(void); void av1_predict_intra_block_facade(MACROBLOCKD *xd, int plane, int block_idx, int blk_col, int blk_row, TX_SIZE tx_size); @@ -27,30 +41,36 @@ void av1_predict_intra_block(const MACROBLOCKD *xd, int bw, int bh, const uint8_t *ref, int ref_stride, uint8_t *dst, int dst_stride, int aoff, int loff, int plane); -#if CONFIG_EXT_INTER +#if CONFIG_EXT_INTER && CONFIG_INTERINTRA // Mapping of interintra to intra mode for use in the intra component static const PREDICTION_MODE interintra_to_intra_mode[INTERINTRA_MODES] = { - DC_PRED, V_PRED, H_PRED, D45_PRED, D135_PRED, - D117_PRED, D153_PRED, D207_PRED, D63_PRED, TM_PRED + DC_PRED, V_PRED, H_PRED, +#if CONFIG_ALT_INTRA + SMOOTH_PRED +#else + TM_PRED +#endif }; // Mapping of intra mode to the interintra mode static const INTERINTRA_MODE intra_to_interintra_mode[INTRA_MODES] = { - II_DC_PRED, II_V_PRED, II_H_PRED, II_D45_PRED, II_D135_PRED, - II_D117_PRED, II_D153_PRED, II_D207_PRED, II_D63_PRED, + II_DC_PRED, II_V_PRED, II_H_PRED, II_V_PRED, +#if CONFIG_ALT_INTRA + II_SMOOTH_PRED, +#else + II_TM_PRED, +#endif + II_V_PRED, II_H_PRED, II_H_PRED, II_V_PRED, #if CONFIG_ALT_INTRA - II_DC_PRED, // Note: Filler value, as there's no II_SMOOTH_PRED. -#endif // CONFIG_ALT_INTRA + II_SMOOTH_PRED, II_SMOOTH_PRED +#else II_TM_PRED -}; -#endif // CONFIG_EXT_INTER -#ifdef __cplusplus -} // extern "C" #endif +}; +#endif // CONFIG_EXT_INTER && CONFIG_INTERINTRA #if CONFIG_FILTER_INTRA #define FILTER_INTRA_PREC_BITS 10 -extern int av1_filter_intra_taps_4[TX_SIZES][INTRA_MODES][4]; #endif // CONFIG_FILTER_INTRA #if CONFIG_EXT_INTRA @@ -59,9 +79,15 @@ static INLINE int av1_is_directional_mode(PREDICTION_MODE mode, return mode != DC_PRED && mode != TM_PRED && #if CONFIG_ALT_INTRA mode != SMOOTH_PRED && +#if CONFIG_SMOOTH_HV + mode != SMOOTH_V_PRED && mode != SMOOTH_H_PRED && +#endif // CONFIG_SMOOTH_HV #endif // CONFIG_ALT_INTRA bsize >= BLOCK_8X8; } #endif // CONFIG_EXT_INTRA +#ifdef __cplusplus +} // extern "C" +#endif #endif // AV1_COMMON_RECONINTRA_H_ |