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authorwolfbeast <mcwerewolf@gmail.com>2018-11-01 10:33:07 +0100
committerwolfbeast <mcwerewolf@gmail.com>2018-11-01 10:33:07 +0100
commit24a83a813641a6500e91f9fcf1ea3ca0aecc047a (patch)
tree5aeea294acacf04bc74a8d947521d05995c8ddf8 /js/src/jit/x86/Assembler-x86.h
parenta2a8c71d7774858db67f51b9c475c5b1d4e43e8f (diff)
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Simplify SIMD conversion from Uint64 to Double.
Diffstat (limited to 'js/src/jit/x86/Assembler-x86.h')
-rw-r--r--js/src/jit/x86/Assembler-x86.h13
1 files changed, 2 insertions, 11 deletions
diff --git a/js/src/jit/x86/Assembler-x86.h b/js/src/jit/x86/Assembler-x86.h
index 3fb5efaff..5939583d9 100644
--- a/js/src/jit/x86/Assembler-x86.h
+++ b/js/src/jit/x86/Assembler-x86.h
@@ -421,20 +421,11 @@ class Assembler : public AssemblerX86Shared
MOZ_ASSERT(dest.size() == 16);
masm.vhaddpd_rr(src.encoding(), dest.encoding());
}
- void vsubpd(const Operand& src1, FloatRegister src0, FloatRegister dest) {
+ void vsubpd(FloatRegister src1, FloatRegister src0, FloatRegister dest) {
MOZ_ASSERT(HasSSE2());
MOZ_ASSERT(src0.size() == 16);
MOZ_ASSERT(dest.size() == 16);
- switch (src1.kind()) {
- case Operand::MEM_REG_DISP:
- masm.vsubpd_mr(src1.disp(), src1.base(), src0.encoding(), dest.encoding());
- break;
- case Operand::MEM_ADDRESS32:
- masm.vsubpd_mr(src1.address(), src0.encoding(), dest.encoding());
- break;
- default:
- MOZ_CRASH("unexpected operand kind");
- }
+ masm.vsubpd_rr(src1.encoding(), src0.encoding(), dest.encoding());
}
void vpunpckldq(FloatRegister src1, FloatRegister src0, FloatRegister dest) {