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authorJiaxun Yang <jiaxun.yang@flygoat.com>2020-05-12 12:40:13 +0800
committerJiaxun Yang <jiaxun.yang@flygoat.com>2020-05-14 16:31:59 +0800
commit77544de5d66a8bf403a9e9db4c0eb7b98c437a65 (patch)
tree6a96a53bdd73735c95242b866243d36ae7f5fe7c /js/src/jit/arm
parent9679f714f7c3a1da7af0ddd1c2005f8f7ffd039b (diff)
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Bug 1330942 - move MemoryAccessDesc::isUnaligned to the ARM/MIPS platform layer
Tag: #1542
Diffstat (limited to 'js/src/jit/arm')
-rw-r--r--js/src/jit/arm/Assembler-arm.cpp12
-rw-r--r--js/src/jit/arm/Assembler-arm.h2
-rw-r--r--js/src/jit/arm/Lowering-arm.cpp4
3 files changed, 16 insertions, 2 deletions
diff --git a/js/src/jit/arm/Assembler-arm.cpp b/js/src/jit/arm/Assembler-arm.cpp
index 1e20da1c8..b231128c5 100644
--- a/js/src/jit/arm/Assembler-arm.cpp
+++ b/js/src/jit/arm/Assembler-arm.cpp
@@ -171,6 +171,18 @@ ABIArgGenerator::next(MIRType type)
return softNext(type);
}
+bool
+js::jit::IsUnaligned(const wasm::MemoryAccessDesc& access)
+{
+ if (!access.align())
+ return false;
+
+ if (access.type() == Scalar::Float64 && access.align() >= 4)
+ return false;
+
+ return access.align() < access.byteSize();
+}
+
// Encode a standard register when it is being used as src1, the dest, and an
// extra register. These should never be called with an InvalidReg.
uint32_t
diff --git a/js/src/jit/arm/Assembler-arm.h b/js/src/jit/arm/Assembler-arm.h
index 8bb754a50..ecfb83b42 100644
--- a/js/src/jit/arm/Assembler-arm.h
+++ b/js/src/jit/arm/Assembler-arm.h
@@ -108,6 +108,8 @@ class ABIArgGenerator
uint32_t stackBytesConsumedSoFar() const { return stackOffset_; }
};
+bool IsUnaligned(const wasm::MemoryAccessDesc& access);
+
static constexpr Register ABINonArgReg0 = r4;
static constexpr Register ABINonArgReg1 = r5;
static constexpr Register ABINonArgReg2 = r6;
diff --git a/js/src/jit/arm/Lowering-arm.cpp b/js/src/jit/arm/Lowering-arm.cpp
index c26680116..b9440816a 100644
--- a/js/src/jit/arm/Lowering-arm.cpp
+++ b/js/src/jit/arm/Lowering-arm.cpp
@@ -613,7 +613,7 @@ LIRGeneratorARM::visitWasmLoad(MWasmLoad* ins)
LAllocation ptr = useRegisterAtStart(base);
- if (ins->access().isUnaligned()) {
+ if (IsUnaligned(ins->access())) {
// Unaligned access expected! Revert to a byte load.
LDefinition ptrCopy = tempCopy(base, 0);
@@ -662,7 +662,7 @@ LIRGeneratorARM::visitWasmStore(MWasmStore* ins)
LAllocation ptr = useRegisterAtStart(base);
- if (ins->access().isUnaligned()) {
+ if (IsUnaligned(ins->access())) {
// Unaligned access expected! Revert to a byte store.
LDefinition ptrCopy = tempCopy(base, 0);